Recently, wide screen displays having an aspect ratio of 16:9 (shown, for example, in FIG. 12(a)) are spreading in the Japanese market. When an ordinary video signal having an aspect ratio of 4:3 (that is 12:9) is applied to a display apparatus having an aspect ratio of 16:9, the displayed picture is horizontally deformed (elongated). As a result, a true circle, for example, is displayed as an ellipse (as shown in FIG. 12(a)). Accordingly, in order to get a correct picture, it is desirable to compress a video signal horizontally as shown in FIG. 12(b). In FIG. 12(b), the picture aspect ratio is 4:3, while the screen aspect ratio is 16:9.
A block diagram of a video signal compression apparatus in accordance with a first exemplary embodiment of the present invention is shown in FIG. 9. A line memory 31 using an SRAM (static random access memory) stores an input video signal in order from the address 0 and when a read address A.sub.n is given, outputs data D.sub.n and D.sub.n+1 for the address A.sub.n and A.sub.n+1, respectively. An address generator 32 includes a counter 34, a multiplier 35 and an adder 36. The counter 34 counts the number of clock pulses and outputs 0, 1, 2, 3, . . . , after being cleared, synchronizing with a horizontal sync signal 103. The multiplier 35 multiplies the output of the counter 34 by a specific value given from the outside. This specific value determines a compression ratio. The adder 36 adds an integer part of the output of the multiplier 35 and the output of the counter 34 and makes a read address A.sub.n of the line memory 31.
An interpolation filter 33 includes a subtracter 37, a multiplier 38 and an adder 39. The subtracter 37 calculates data (D.sub.n+1 -D.sub.n). The multiplier 38 multiplies (D.sub.n+1 -D.sub.n) by a decimal part of the output of the multiplier 35. The adder 39 adds the data D.sub.n and the output of the multiplier 38 and outputs the sum. The output of the adder 38 is a compressed video signal as explained below.
The performance of a video signal compression apparatus in accordance with the prior art is explained using a time chart shown in FIG. 10.
(a) The data of the input video signal is stored in the line memory 31 in order from address 0. PA0 (b) The multiplier 35 calculates the products of the output 0, 1, 2, 3, . . . . , of the counter 34 and a specific value (1/3 in this case). The calculated result is separated to an integer part and a decimal part. PA0 (c) The read address A.sub.n is made from the sum of the integer part and the output of the counter 34. PA0 (d) When the read address A.sub.n is inputted, the line memory 31 outputs the data D.sub.n and D.sub.n+1. PA0 (e) The subtracter 37 calculates data (D.sub.n+1 -D.sub.n). PA0 (f) The multiplier 38 multiplies the data (D.sub.n+1 -D.sub.n) by the decimal part separated from the output of the multiplier 35. PA0 (g) The adder 39 adds the data D.sub.n and the output of the multiplier 38 and outputs a compressed video signal.
FIG. 11(a) shows a video signal before compression, that is an input video signal and FIG. 11(b) shows a video signal after compression, that is an output signal of the video signal compression apparatus. The axis of abscissa shows time and the axis of ordinate shows signal level.